General info

This course runs from 08:30 to approximately 17:30, and may occasionally continue until 18:00. It includes exercises during the day as well as in the evening. At the end of the course, participants can receive an official certificate.

The course is aimed at system and IC designers, CMOS process engineers, engineers working in IC simulation, verification, testing, reliability, and design methods, as well as engineers involved in electronic product development and others who need a thorough understanding of the complete development chain of CMOS integrated circuits and products.

The main objectives are to understand the full design and development cycle, from basic transistor and library-cell layouts to complete systems on a chip; acquire detailed technical knowledge of CMOS physics and fabrication; understand the physical issues that determine optimum design performance; gain the knowledge required for low-power, robust, and reliable chip operation; and place each participant’s own work in a broader technical perspective.

The course begins with the basic principles of CMOS, including device physics, operation, transistor characteristics, current expressions, capacitances, geometry effects, temperature behavior, short-channel effects, subthreshold operation, and leakage mechanisms.

After a discussion on wafer creation and properties, the CMOS technology section reviews advanced lithography methods, basic CMOS processing steps, and process cross sections ranging from early nMOS technology to advanced planar CMOS processes, FinFET processes, and Gate-All-Around processes, such as nano-sheet, nano-wire and fork-sheet processes)

The CMOS design section gives a broad overview of electrical, logic, library, and layout design, together with selected analog and mixed-signal topics. This is followed by a detailed CMOS memories section, covering SRAM, DRAM, HBM, ROM, PROM, EEPROM, NAND and NOR flash memories, as well as both stand-alone and embedded memory architectures.

The section on VLSI and ASICs discusses the design flow, hierarchy levels, IP cores, reuse, standard-cell design, and ASIC development. A practical design example follows a signal processor from system level down to layout level.

A substantial part of the course is devoted to low-power design and power-reduction techniques. This section covers active and standby power, leakage mechanisms, technology options for reducing power, and design methods for minimizing both switching power and leakage power.

The section on IC robustness addresses reliability and signal-integrity issues such as latch-up, punch-through, ESD protection, hot-carrier degradation, electromigration, NBTI, supply and substrate noise, power integrity, back-side power distribution, on-chip decoupling, crosstalk, noise margins, EMI, EMC, soft errors, and variability.

The course also provides a comprehensive overview of testing, debugging, failure analysis, yield, and packaging, including IC test methods, DfT, BIST, basic yield models, extensive (3D-)package characteristics and trends, diagnostic methods, advanced failure analysis techniques, repair, and focused ion beam methods.

Finally, scaling trends, roadblocks, and “What’s Next?” examines scaling toward advanced technology nodes, speed and power trends, design and manufacturing costs, future roadblocks, possible solutions, and the continuing evolution beyond traditional Moore’s law scaling.

The course includes many practical examples, problems, and common pitfalls of integrated-circuit design, together with exercises during both daytime and evening sessions. On request, the course can be concluded with a final examination and a certificate for participants who successfully pass.

The course includes a copy of the most recent edition of the book Nanometer CMOS ICs.