General info

This course runs from 08:30 to approximately 17:30, and may occasionally continue until 18:00. It includes several exercises during the day, but there is no final examination. At the end of the course, participants receive an official certificate.

The course is designed as a comprehensive tutorial on selected topics in state-of-the-art CMOS integrated circuits for engineers working in R&D centers of semiconductor lithography and fabrication companies, such as ASML, Applied Materials, TSMC, GlobalFoundries, Samsung, and Micron Technology.

The main objectives are to familiarize participants with commonly used semiconductor terminology, provide a solid understanding of the complete chip development process, improve communication with technical colleagues, suppliers, and customers, and place each participant’s own work in a broader semiconductor context. By understanding how their individual contribution fits into the complete development process, participants can also gain a stronger sense of involvement and motivation.

The course starts with an introduction to the evolution of electronics, the basic concepts and terminology of integrated circuits, and an overview of the complete chip development flow from design to application.

The section on wafers and transistors covers substrates, wafers, basic transistor operation, and CMOS technology. This is followed by lithography, with an overview of modern lithography techniques and tools, including multiple patterning and EUV, and their relationship to IC design and CMOS processing.

The fabrication section gradually introduces the process layers and manufacturing steps used to build a chip, starting with a simple five-mask process from the 1970s and progressing through advanced FinFET technologies to gate-all-around devices and nanosheet, nanoribbon, and nanowire transistors.

The section on memories explains the main memory types, architectures, and memory cells, including SRAM, DRAM, EPROM, and flash memory, with particular attention to multilevel and multilayer 3D NAND flash technologies.
The design section provides a basic understanding of transistor layout, design methodologies, libraries and library cells, and the relationship between design complexity, lithography, and process technology.

The course also covers testing, yield, and failure analysis, including basic chip testing, test complexity, yield models, random and systematic yield loss, design for manufacturability, and its relationship to lithography.

The packaging section discusses the physical, electrical, and thermal characteristics of packages, their influence on overall system size, and the use of advanced 3D packaging techniques.

Finally, What’s Next? addresses the roadblocks to further scaling, the possible end of Moore’s law, time-to-market, design and manufacturing costs, and the combination of microelectronics with micro-, nano-, and biotechnology, such as MEMS and biochips, to create highly integrated systems.

The course includes a copy of the most recent edition of the book Nanometer CMOS ICs