Contents
PART 111
PREFACE to PART 112
CHAPTER 1 The Electronics (R)evolution15
1.1 Some history15
1.2 Chip evolution17
1.3 Impact of the chip on our society21
CHAPTER 2 What is a chip?31
2.1 Chips are all around us31
2.2 Why cannot everything be done with a single chip?32
2.3 What’s on a chip?33
2.4 From required functionality to required operations34
2.5 Basic building blocks on a chip37
2.6 Similarity between chip floor plan and city plan38
2.6.1 Similarity between building a house and creating a chip41
2.6.2 However...45
2.7 Conclusion46
CHAPTER 3 Basic concepts and definitions47
3.1 Introduction47
3.2 The MOS transistor48
3.3 The world is analog50
3.4 From decimal to binary numbers51
3.5 Analog to digital conversion53
3.6 Wireless (RF) communication56
3.7 Mixed signal circuits61
3.8 Memories62
3.9 Hardware and software, architecture, instructions and algorithms64
3.10 Conclusion65
CHAPTER 4 The chip development cycle67
4.1 Introduction67
4.2 Design68
4.3 Substrates (wafers)69
4.4 Fabrication71
4.5 Testing and packaging77
4.6 Conclusion78
PART 281
PREFACE to PART 282
CHAPTER 1 Digital circuits and IP85
1.1 Digital circuits85
1.2 Basic functions and logic gates87
1.2.1 The inverter (NOT gate) and driver circuit88
1.2.2 The AND and NAND gate89
1.2.3 The OR and NOR gate90
1.2.4 Combined gates92
1.2.5 Drivers (or buffers)93
1.3 Basic logic (digital) operations94
1.3.1 Introduction94
1.3.2 Binary addition and building an adder94
1.3.3 Building a multiplier97
1.4 Synchronous designs and flip-flops99
1.5 Digital core and chip design101
1.5.1 Example of synthesis from VHDL description to layout105
1.6 Gate arrays and programmable logic devices109
1.7 Conclusion111
CHAPTER 2 Memory circuits and IP113
2.1 Introduction113
2.2 General architecture of a memory115
2.3 Volatile memories119
2.3.1 Introduction119
2.3.2 Static Random Access Memory (SRAM)119
2.3.3 Dynamic Random-Access Memory (DRAM)120
2.4 Non-volatile memories123
2.4.1 Introduction123
2.4.2 Read-Only Memory (ROM)123
2.4.3 Programmable Read-Only Memory (PROM)124
2.4.4 Erasable Programmable Read-Only Memory (EPROM, EEPROM)125
2.4.5 Flash memories127
2.4.6 Non-volatile RAM and battery RAM132
2.4.7 Alternative non-volatile memories and emerging technologies133
2.5 Memory interfaces136
2.6 Stand-alone versus embedded memories136
2.7 Classification of the various memories137
2.8 Memory yield137
2.9 Conclusion137
CHAPTER 3 Analog IP, Interfaces and Integration141
3.1 Introduction141
3.2 Analog circuits and IP141
3.3 Chip interfaces145
3.3.1 Connection145
3.3.2 Protection146
3.3.3 Interface147
3.4 Mixed-signal ICs and integration150
3.5 Conclusion153
CHAPTER 4 Wafers and Transistors155
4.1 Introduction155
4.2 What is an n-type and what is a p-type semiconductor?156
4.3 Basic MOS transistor architectures158
4.4 Different substrates (wafers) as starting material161
4.4.1 Wafer fabrication161
4.4.2 Wafer sizes161
4.4.3 Bulk and epitaxial silicon wafers161
4.4.4 Crystal orientation of the silicon wafer162
4.4.5 Silicon-on-insulator (SOI)164
4.5 Conclusion165
CHAPTER 5 Lithography167
5.1 Lithography basics167
5.2 Resolution enhancement techniques170
5.3 Lithographic alternatives beyond 30 nm175
5.4 Mask cost reduction techniques for low-volume production182
5.5 Conclusion183
CHAPTER 6 Fabrication185
6.1 Introduction185
6.2 Basic process steps186
6.2.1 Deposition186
6.2.2 Etching187
6.2.3 Oxidation188
6.2.4 Diffusion and ion implantation190
6.2.5 Planarization191
6.3 Basic MOS technologies194
6.3.1 The basic silicon-gate nMOS process194
6.3.2 The basic Complementary MOS (CMOS) process197
6.3.3 CMOS processes below 32 nm198
6.4 CMOS technology beyond 10 nm200
6.4.1 Devices (transistors)200
6.4.2 Interconnects203
6.5 Conclusion204
CHAPTER 7 Chip performance and power207
7.1 Introduction207
7.2 The need for less power everywhere207
7.3 Impact of scaling on power and performance209
7.3.1 Transistor scaling209
7.3.2 Interconnection scaling212
7.3.3 Scaling impact on chip performance and power parameters215
7.4 Battery technology summary217
7.5 Conclusion219
CHAPTER 8 Testing and Yield221
8.1 Introduction221
8.2 Testing222
8.2.1 Test categories222
8.2.2 Design for testability224
8.2.3 Testing of mixed-signal circuits227
8.3 Yield228
8.3.1 Influence of production environment228
8.3.2 A simple yield model and yield control230
8.4 Design for manufacturability237
8.5 Towards chiplet design to reduce manufacturing costs239
8.6 Conclusion241
CHAPTER 9 Failure Analysis243
9.1 Introduction243
9.2 Traditional debug, diagnosis and failure analysis techniques243
9.3 More recent failure analysis techniques245
9.3.1 Time-Resolved Photo Emission Microscopy (TR-PEM)246
9.3.2 Laser Scanning Optical Microscopy (SOM) techniques247
9.3.3 Scanning Electron-Beam Microscopy (SEM) techniques248
9.3.4 E-beam microscopy in stacked die testing and failure analysis249
9.4 Observing the failure250
9.5 Circuit-editing techniques252
9.6 Conclusion253
CHAPTER 10 Packaging255
10.1 Introduction255
10.2 Package categories255
10.3 Die preparation and packaging process flow256
10.4 Electrical aspects of packaging259
10.5 Thermal aspects of packaging260
10.6 Quality and Reliability aspects262
10.6.1 Reliable bonding262
10.6.2 Quality of packaged dies263
10.6.3 Reliability of packaged dies264
10.7 Trends in packaging technology266
10.8 Advanced package technologies271
10.9 Conclusion275
CHAPTER 11 And, what is next?277
11.1 Introduction277
11.2 Scaling trends and limits: more of Moore (or: more Moore)277
11.2.1 Introduction277
11.2.2 System complexity and Heterogeneous Integration279
11.2.3 Design complexity279
11.2.4 Transistor and interconnect complexity280
11.2.5 Fabrication complexity282
11.2.6 Package complexity282
11.2.7 Test, debug and failure analysis complexity283
11.2.8 Time-to-market283
11.2.9 Breaking down the cost of chip development284
11.2.10 Conclusion293
11.3 The next decade:
295
11.3.1 Introduction295
11.3.2 Sensors, actuators, and micro/nanosystems295
11.3.3 Nanotechnology and Nanosystems302
11.3.4 Conclusion306
References307
Index317